Variations in Chip Manufacture: Modeling for Control and Design

James Chung and Duane Boning
MIT EECS and MTL

Monday, May 6, 1996
4:00 PM (3:30 refreshments)
Edgerton Hall, Room 34-101
EECS Colloquium

Abstract

The foundation for the electronics revolution has been silicon VLSI technology. Silicon CMOS devices are not the fastest, but their manufacturability, reliability, and low cost per bit have proved decisive. Their great manufacturability is based on the ability to model the device and interconnect behavior (enabling sophisticated circuit designs) and then to fabricate millions of nearly identical devices on a chip that behave in substantial agreement with the model predictions. The key to this manufacturability is the ability to control parameter variation and to account for its effect in both semiconductor processing and circuit design.

The control and understanding of variation becomes more difficult as device dimensions shrink and chip and process complexity increase. We will present methods being developed to model known and emerging aspects of chip manufacturing variation, including spatial variations across the wafer and across each chip within the wafer. We will describe the experimental and measurement methods, and the statistical analysis approaches which can identify sources of device and interconnect variation. Application to key process technologies, such as fine line photolithography and chemical mechanical polishing, will be presented. Such variation models will impact not only process optimization and control, but also circuit design practices in tomorrow's VLSI technologies.

URL of this page: http://www-eecs.mit.edu/AY95-96/events/54.html
Created: Apr 23, 1996 | Modified: Jun 25, 1997
This announcement is from the MIT EECS 1995-96 archive. | Current events
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